Xilinx 24/30

Apr 25, 20194 min read

Run Hello World on a ZC702

This post shows how run Hello World on a Xilinx ZC702. It covers: creating a design in Vivado, exporting the design to the SDK and...

Apr 24, 20193 min read

Xilinx SDK Internal Error: The folder "C:\....\.metadata" is read-only

This post discusses the Xilinx SDK Internal Error: The folder "C:\....\.metadata" is read-only. Quick Workaround Remove spaces in your...

Apr 19, 201911 min read

Getting Started with Vivado High-Level Synthesis Transcript

This is a transcript of the Xilinx Quick Take video Getting Started with Vivado High-Level Synthesis at [link]. Transcript Hello and...

Apr 14, 201911 min read

Xilinx's "Creating an AXI Peripheral in Vivado": Transcript, Screenshots & Commentary

This post presents a transcript + screenshots of "Creating an AXI Peripheral in Vivado" from Xilinx. It is intended to reinforce learning...

Apr 12, 20191 min read

Zynq-7000 QSPI Flash Support Guide from Xilinx

This post lists links to a QSPI Flash Support Guide for Zynq-7000 that Xilinx released. It also presents a link to the guide in case the...

Apr 11, 20191 min read

What Should the Board Trace Delay Be if the Clock and Data Traces have the same Length?

A good post about what board trace delay should be if the clock and data traces have the same length. "board trace delay in source...