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Lattice Diamond 3.10 SP3 File Extensions
This post lists all the file extensions used by Lattice Diamond 3.10 SP3. File Extension: File Use _sc: Schematic Editor log file _sy:...
Xilinx BSP Documentation
This post lists a link to Xilinx's "BSP documentation." It also lists links to the "embeddedsw" git where all of the "standalone code" is...
Mobile Networks for IoT
This post lists some of the wireless networks that can support IoT and links to additional resources. The list is not exhaustive. Legacy...
IoT Protocols Supported by AWS IoT, Microsoft Azure IoT Central and Google Cloud IoT Core
This post lists the IoT protocols supported by Amazon AWS' IoT, Microsoft Azure's IoT Hub and Google Cloud's IoT Core as of May 28th...
Reboot Windows 7 Remotely over RDP
This post shows how to restart Windows 7 over RDP. A. Click Windows B. Click Windows Security C. Expand the red Power Off button D. Click...
Open Links from Word 2016 in Chrome Instead of IE on Win 7 SP1
This post shows how to open links from Word 2016 in Chrome instead of IE on Win 7. Versions Used Windows 7 SP1 Microsoft Office Home and...
Why do I need to run "Create HDL Wrapper..."
This post lists why a Vivado IP integrator a block diagram must be wrapped in an HDL wrapper, short answer: "because a BD (block design)...
Vivado Constraint Wizard Step-by-Step
This post presents how to run the Vivado constraint wizard step-by-step. It presents steps from the Xilinx Quick Take video @ [link] +...
Notes on the "Using the Vivado Timing Constraint Wizard" QuickTake Video from Xilinx
This post lists notes on the "Using the Vivado Timing Constraint Wizard" QuickTake Video from Xilinx. It includes info highlights, links...
Zynq-7000 + AXI Slave with Interrupt Hello World on a ZC702
This post lists step-by-step instructions for creating an AXI slave with an interrupt using Vivado HLS, integrating the slave into a...
Zynq-7000 + AXI Slave Hello World
This post shows how to create a Xilinx Zynq-7000 + AXI slave in Vivado 2018.2 and read/write the AXI slave from the ARM9 of the Zynq-7000...
Set up the JTAG and Serial Port on the ZC702
This post shows you how to connect the JTAG and serial port of the ZC702, where to get the USB-to-serial port driver and how to configure...
Supported Altium File Type Extensions
This post lists all the file type extensions Altium supports and a short description of what they are. The List How to Look this Up Step...
Run Hello World on a ZC702
This post shows how run Hello World on a Xilinx ZC702. It covers: creating a design in Vivado, exporting the design to the SDK and...
Xilinx SDK Internal Error: The folder "C:\....\.metadata" is read-only
This post discusses the Xilinx SDK Internal Error: The folder "C:\....\.metadata" is read-only. Quick Workaround Remove spaces in your...
Tools to Create How To Videos on Windows 7
This post lists some tools that can be used to help create demos. Magnify Clicks Use the Windows 7 Magnifier to magnify where you click....
Getting Started with Vivado High-Level Synthesis Transcript
This is a transcript of the Xilinx Quick Take video Getting Started with Vivado High-Level Synthesis at [link]. Transcript Hello and...
Lattice Semiconductor's "senseAI": Trascript, Screenshots & Commentary
This post presents a transcript + screenshots of "senseAI" from Lattice Semiconductor. It was built to provide an easy reference to the...
Xilinx's "Creating an AXI Peripheral in Vivado": Transcript, Screenshots & Commentary
This post presents a transcript + screenshots of "Creating an AXI Peripheral in Vivado" from Xilinx. It is intended to reinforce learning...
Links and Tips to Create a Transcript from Online Video
To create a transcript of an online video that doesn't include one you can use: Audacity, OpenShot Video Editor and YouTube...
Zynq-7000 QSPI Flash Support Guide from Xilinx
This post lists links to a QSPI Flash Support Guide for Zynq-7000 that Xilinx released. It also presents a link to the guide in case the...
What Should the Board Trace Delay Be if the Clock and Data Traces have the same Length?
A good post about what board trace delay should be if the clock and data traces have the same length. "board trace delay in source...
Where are the Vivado I/O Planning Tools?
This post lists the answer to where the Vivado I/O Planning tools are. The I/O Planning option can be seen in both the Tools menu and the...
A Good Constraint Conversation
This Xilinx community forums link contains some good information on what's actually needed to constrain I/O (embedded in a conversation...
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