May 18, 20183 min readIntegrate a QSPI using PetaLinux Tools Part 2Why are there two ranges here: reg = <0x0 0xff0f0000 0x0 0x1000 0x0 0xc0000000 0x0 0x8000000>;?
Apr 24, 20181 min readChange the Boot Mode of the Xilinx Zynq UltraScale+ MPSoC from XSCTtargets -set -nocase -filter {name =~ "*PSU*"}; stop; mwr 0xff5e0200 0x0100; rst -system
Apr 22, 20188 min readBoot Linux on the Zynq UltraScale+ MPSoC over JTAG using PetaLinux Tools1. Upon reset, the device mode pins are read to determine the primary boot device to be used: NAND, Quad-SPI, SD, eMMC, or JTAG.
Mar 25, 20182 min readWhat is the Voltage of the UART on my Zynq UltraScale+ MPSoC Board?Look at the schematic to see which MIO UART TX and RX are connected to. Consult this table. Find the corresponding VCC_PSIO pin and what vo
