This post lists a XCVU9P-L2FLGA2104E decode and its features. This part is used on the AMD Virtex UltraScale+ FPGA VCU118 Evaluation Kit @ https://www.xilinx.com/products/boards-and-kits/vcu118.html.
XCVU9P-L2FLGA2104E Decode and Its Features
XC V U 9 P -L2 F L G A 2104 E
XC | Commercial Grade |
V | Virtex |
U | UltraScale |
9 | Value Index |
P | UltraScale+ |
-L2 | Low Power |
F | |
L | Lid SSI |
G | RoHS 6/6 w/ Exemption 15 |
A | Package Designator |
2104 | Package Pin Count |
E | Extended (Tj = 0 degC to +110 degC) |
Virtex UltraScale+ FPGA Feature Summary
VU9P | |
System Logic Cells | 2,586,150 |
CLB Flip-Flops | 2,364,480 |
CLB LUTs |
|
Max. Distributed RAM (Mb) | 36.1 |
Block RAM Blocks | 2,160 |
Block RAM (Mb) | 75.9 |
UltraRAM Blocks | 960 |
UltraRAM (Mb) | 270 |
HBM DRAM (GB) | – |
CMTs (1 MMCM and 2 PLLs) | 30 |
Max. HP I/O(1) | 832 |
Max. HD I/O(2) | 0 |
DSP Slices | 6,840 |
System Monitor | 3 |
GTY Transceivers 32.75 Gb/s(3) | 120 |
GTM Transceivers 58.0 Gb/s | 0 |
100G / 50G KP4 FEC | 0 |
Transceiver Fractional PLLs | 60 |
PCIE4 (PCIe Gen3 x16)(4) | 6 |
PCIE4C (PCIe Gen3 x16 / Gen4 x8)(4)(5) | 0 |
150G Interlaken | 9 |
100G Ethernet w/RS-FEC | 9 |
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